1. Field of the Invention
The present invention relates to a processing unit, and, more particularly, to a processing unit for a whitener encoder used for a wireless LAN.
2. Description of the Prior Art
A wireless LAN (local area network) is set forth in a standard being provided by the IEEE 802.11 Committee. An algorithm on the white encoder is described in a publication, "Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications," Draft Standard IEEE 802.11, Jan. 26, 1996 (P 802.1103), by Institute of Electrical and Electronics Engineers, Inc., pp. 179-180, 183-184, and 189.
First, a transmission frame used by the wireless LAN is described in FIG. 7. A start frame delimiter (SFD) 54 is sent following a preamble 53 in which "1" and "0" are repeated. After a header 55 containing information indicating transmission data length and a transmission frame is sent following SFD 54 informing a receiver that valid data follows, transmission data 56 is sent.
The transmission data 56 has a variable length. A whitener encoder inserts and sends one stuff bit 52 in every 32 bits. To suppress DC bias in a transmission frame, the whitener encoder inverts the transmission data 56 during certain 32 bits segments.
The stuff bit 52 is set to a "1" bit and inserted before the 32-bit interval in which the transmission data 56 is bit inverted. This enables the receiver to receive proper data by bit inverting the transmission data 56 again when the stuff bit 52 is a "1" bit. Here, a cyclic redundancy check (CRC) 57 for error checking is appended to the end of the transmission frame.
FIG. 8 is a block diagram showing the configuration of a conventional processing unit. The processing unit in the figure is configured according to the whitener encoder algorithm described in IEEE 802.11. The operation of a conventional processing unit is described below by referring to FIGS. 7 and 8.
First, the parallel format input transmission data is converted into a serial data format by a parallel-serial converter circuit 11. Then, the transmission data converted into the serial data format is randomized by a scrambler 12.
The scrambled data is input into an n-bit shift register 13. Here, n=32 is assumed. The shift register 13 takes out data from the transmission data 56 in the transmission frame in every 32 bits. Then, an adder circuit 31 weighs and adds the 32-bit data thus taken out by bit. This is to execute "bias.sub.-- next.sub.-- block=Sum {weight (b (0)), . . . , weight (b (32))}" in the above-mentioned algorithm of IEEE 802.11.
b(1) to b(32) indicate the data taken out by the 32-bit shift register 13. b(0) is the stuff bit 52. This stuff bit 52 is a bit inserted in a frame in every 32 bits by a stuff bit insertion circuit 14. The initial value of the stuff bit 52 is b (0)=0.
The weight is +2 when the transmission data 56 is "1," and -2 when it is "0". For example, weight (b (1))=+2 for b (1)=1, while weight (b (1))=-2 for b (2)=0.
The adder circuit 31 is reset when the frame transmission is started, and also reset after calculation for every 32 bits. The resetting causes the adder circuit 31 to have a value of "0".
Here, it is assumed that the result calculated by the adder circuit 31 is "bias," and the result calculated by the adder circuit 32 is "accum." Then, a comparator circuit 33 determines whether or not bias*accum&gt;0. This means to execute "If {[accum*bias.sub.-- next.sub.-- block&gt;0] then . . . }" in the algorithm. The comparator circuit 33 has an output of "0" if the determination result is bias*accum&gt;0, and an output of "1" if the determination result bias*accum&lt;0.
When the output of the comparator circuit 33 is "0", bit inversion is performed by a bit inverter circuit 15 for the data in the interval of 32 bits used for the calculation of bias when each bit is sent out. This is to execute "Invert {b (0), . . . , b (N)}" in the algorithm. On the other hand, when the output of the comparator circuit 33 is "1", the bit inversion is not performed.
When the output of the comparator circuit 33 is "0", inversion is performed on the output of the adder circuit 31 (bias) by a sign inverter circuit 34. This is to execute "bias.sub.-- next.sub.-- block=-bias.sub.-- next.sub.-- block" in the above algorithm. On the other hand, when the output of the comparator circuit 33 is "1", the bit inversion is not performed.
As described above, the adder circuit 31 adds transmitted data in every certain interval of 32 bits, and the adder circuit 32 adds the results obtained by the adder circuit 31. The result from the adder circuit 32 is saved in a register 35. Then, the comparator circuit 33 compares the value of the adder circuit 31 with that of the register 35 in every interval of 32 bits. According to the result of the comparator circuit 33, the sign inverter circuit 34 operates to invert the sign of the result of the adder circuit 31, and the bit inverter circuit 15 to invert the transmitted data "1" and "0". The output of the bit inverter circuit 15 becomes transmitted data TX.
Operation of a conventional whitener encoder is described by referring to the timing charts of FIGS. 9 and 10, and the block diagram of FIG. 8. FIGS. 9 and 10 show an example where 89h ("h" indicating a hexadecimal number, the same applying to the following) as a header (section of intervals A1 and A2 of FIG. 9), data of 75h, E7h, and B6h are sequentially transmitted from the least significant bit (hereinafter called "LSB"), and 19h, 59h, 05h, 31h, 26h, B1h, 9Ah, and 4Ch are transmitted as the transmitted data after scrambling (section of B1, C1, B2 and C2 of FIGS. 9 and 10) from LSB. For example, when 19h is transmitted from LSB, it is transmitted as "10011000".
Although in FIGS. 9 and 10 data in the interval A1 are not depicted, it is the same as the data in the interval A2. Data in an interval B1 are shifted 32 bits by the 32-bit shift register 13, and transmitted as transmitted data in an interval B2. Similarly, data in an interval C1 is transmitted in an interval C2.
Such shifting by 32 bits occurs because transmission should be performed after determining whether data during an interval of 32 bits is bit inverted after calculating weight based on the data according to the weight calculation method, which is described later.
The adder circuit 31 adds data in the interval of 32 bits with weight. The weight is +2 when the data is "1", and -2 when it is "0". For example, when 19h described above is added with the weight, it is +2-2-2+2+2-2-2-2=-4.
In timing (1) of FIG. 9, since there are 19 "1" bits and 13 "0" bits in the interval A1, the adder circuit 31 provides a result of addition of (+2.times.19)+(-2.times.13)=+12. For the interval A1 or the header section, the result of the adder circuit 31 is accumulated in the register as it is.
In timing (2) of FIG. 9, the adder circuit 31 adds data in the interval B1 including the stuff bit SB. Here, since there are 12 "1" and 21 "0", the result is (+2.times.12)+(-2.times.21)=-18.
In addition, in this timing, the comparator circuit 33 compares the addition result of the adder circuit 31 with the value of the register 35. In this case, since the output of the adder circuit 31 multiplied by the output of the register 35 is less than zero, no signal for inverting the data is output to the sign inverting circuit 34 and the bit inverting circuit 15.
In FIG. 9, the output of the comparator circuit 31 is "1". In other words, since the data inversion is not performed, the output of the sign inverting circuit 34 is "-18", and the bits in the interval B1 is transmitted in the interval B2 as it is without bit inversion. The adder circuit 32 adds the output "-18" of the sign inverting circuit 34 and the output "+12" of the register 35, and obtains a value of -6. The addition result of the adder circuit 32 is accumulated in the register 35.
Similarly, in timing (3) of FIG. 10, the adder circuit 31 adds data in an interval C1 including the stuff bit. Here, since there are 14 "1" bits and 19 "0" bits, the result is (+2.times.14)+(-2.times.19)=-10. In addition, in this timing, the comparator circuit 33 compares the addition result of the adder circuit 31 with the value of the register 35. In this case, since there is provided a result of the output "-10" of the adder circuit 31 multiplied by the output "-6" of the register 35 is greater than zero, the comparator circuit 33 outputs a signal for inverting the data to the signal inverting circuit 34 and the bit inverting circuit 15.
In FIG. 10, the comparator circuit 33 has the output of "0". That is, since the data is inverted, the sign inverting circuit 34 has an output of +10, and transmitted data in the interval C2 is bit-inverted data in the interval C1. The adder circuit 32 adds the output "+10" of the sign inverting circuit 34 and the output "-6" of the register 35, and obtains a value of "+4". The result of the adder circuit 32 is accumulated in the register 35.
Since the stuff bit SB is "1" in an interval in which the transmitted data is bit inverted, the receiver checks to determine whether or not the stuff bit SB is "1", and, if so, inverts subsequent 32 bit data again, and returns them.
The effect of suppression of DC bias by the whitener encoder is described. For example, if the interval C2 is not inverted, the output value of the register 35 after the completion of the interval C2 becomes +12-18-10=-16, so that the transmitted data are shifted toward "0". Then, when the interval C2 is inverted, the value of the register becomes +12-18+10=+4 as described above. In this case, it is reversely shifted towards "1" but not significantly. Thus, the DC bias on the transmitted data can be suppressed by adjusting the number of "1" and "0" in the transmitted data.
As described above, the conventional unit comprises, in addition to a shift register and a stuff bit insertion circuit, two adder circuits for calculating weight, a sign inverting circuit for inverting the result of weight calculation, a register for holding the results of weight calculation in the past, and a comparator circuit for determining whether or not the transmitted data is inverted. Thus, one disadvantage is that the circuit configuration of the processing unit is large. The size of the circuit configuration is described in the following.
First, a description is given for the internal configuration of two adder circuits 31 and 32. An example of the configuration of the adder circuit 31 is shown in FIGS. 11-17. In these figures, similar components are designed by like references.
Input terminals are terminals d15-d28 shown in FIG. 11, terminals d0-d10 shown in FIG. 14, a terminal d29 shown in FIG. 16, and terminals d11-d14 and d31 shown in FIG. 17. In addition, output terminals designated by "&gt;&gt;" in these figures are assumed to be connected to the input terminals with the same references as the output terminals and designated by "&gt;&gt;."
Furthermore, a terminal SUM of FIG. 17 is a 6-bit bus type output terminal, and shown by a thick line for convenience. One bit of the 6-bit terminal SUM of FIG. 17 leads to the input of FIG. 17 from the output of FIG. 15.
The adder circuit 31 with such a configuration performs the operation described above. It will be obvious that an equivalent circuit may be configured by using various gates. The adder circuit 31, configured as shown in FIGS. 11-17, has about 330 gates.
An example of the configuration of the adder circuit 32 is shown in FIG. 18. The adder circuit 32 comprises two input terminals dina and dinb, and an output terminal dout. The input terminals dina and dinb are of a 6-bit bus type, while the output terminal dout is of a 7-bit bus type. All of them are indicated by thick lines for convenience. It is assumed that the most significant bit of seven bits of the output terminal dout is not used, and the remaining six bits are used. Here, the adder circuit 32 shown in the figure has about 39 gates.
The above-mentioned conventional processing unit comprises, in addition to these adder circuits 31 and 32, a register 35 and comparator circuit 33. The register has about 34 gates, while the comparator circuit 33 has about 60-70 gates.
Therefore, the conventional unit has as many as 330+39+34+60=463 gates in total for the adder circuits 31 and 32, the register 35 and the comparator circuit 33, and consequently the circuit is very large.